1. Field of the Invention
Embodiments of the present invention relate to methods and apparatus for boosting a voltage when power is turned on (“power-on”). More particularly, embodiments of the invention relate to latch-up free voltage boosting methods and apparatuses for stably boosting voltages without triggering latch-up.
2. Description of the Related Art
Generally, a peculiar state called latch-up may occur in a device having a complementary metal oxide semiconductor (CMOS) structure. Latch-up is a parasitic phenomenon that may occur when a parasitic thyristor, e.g., silicon controlled rectifier (SCR), at a PNPN junction inherently existing in a CMOS chip causes over-current to flow. Depending on the circuitry, the amount of current produced may be large enough to permanently destroy a chip including the CMOS structure. Latch-up generally occurs when input and output voltages exceed a rated level so that large current flows through an internal component, or when a power voltage exceeds the rated level so that the internal component falls into a breakdown state. Once the chip falls into a latch-up state, the latch-up state may be continuously maintained until power is turned off (“power-off”) due to the structure of the thyristor. Therefore, the chip may be permanently destroyed.
To perform a variety of functions, the CMOS chip may be designed such that it operates using voltages of various levels. When power is initially supplied to the CMOS chip from the outside, the CMOS chip may generate various voltages to be used inside the CMOS chip in sequence or in parallel by boosting a power voltage provided from the outside. When the voltages applied to respective terminals of the PNPN junction are different from one another, latch-up may occur according to the sequence in which the various voltages are applied to the respective terminals.